High-Performance Computing (HPC) is entering a new phase where computer designs will be driven by the goal of minimizing power consumption. Performance per Watt is the new major metric for measuring progress in new computer designs. Performance improvements realized by new parallel architectures depend primarily on two factors: the level of parallelism and minimizing data movement. These have become the two major factors governing performance because of the necessary flat-lining of clock rates (to keep power requirements manageable) and the growing gap between microprocessor technology and memory structures/bandwidth. These, in turn, rely on the optimal use of multicore microprocessors as the primary means by which performance is improved. Consequently, this will require dramatic changes in system architectures, which will force new methods of use, including programming and system management. HPC is now faced with the need for new effective means of sustaining performance growth as microprocessor technology advances through rapid expansion of multicore processors, with anticipated structures of hundreds of millions of cores by the end of this decade, which will have the potential of delivering exascale performance (1000 times today's emerging petascale computers). This presentation will discuss: (i) the driving trends and issues of this new phase in HPC, and (ii) the major challenges that must be addressed to achieve the goal of delivering power-efficient exascale computers. Achieving sustained exascale performance in a 20MW power envelope requires significant power reduction beyond what will be provided by current technology scaling.
