RipTide: A Programmable, Energy-Minimal Dataflow Compiler and Architecture

Souradip Ghosh, Carnegie Mellon University

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Emerging sensing applications create an unprecedented need for extreme energy efficiency in general-purpose processors. To achieve useful multi-year deployments on a small battery or energy harvester, these applications must avoid off-device communication and instead process most data locally. Recent work has proven ultra-low-power (ULP) coarse-grained reconfigurable arrays (CGRAs) as a promising architecture for this domain. Unfortunately, prior ULP designs require hand-written assembly and can only accelerate a fraction of program execution, and other CGRAs target high-performance applications that face different goals and challenges. We introduce RipTide, a co-designed compiler and CGRA architecture targeting high programmability and extreme energy efficiency. RipTide provides a rich set of control-flow operators, letting it support arbitrary control flow and memory access on the CGRA fabric. RipTide implements these primitives without tagged tokens to save energy; this requires careful memory ordering analyses in the compiler to guarantee correctness. We present an ordering graph abstraction and optimize ordering constraints using a path-sensitive transitive reduction and dataflow analysis techniques. RipTide further saves energy and area by offloading most control operations into its programmable on-chip network, where they can re-use existing network switches. RipTide's compiler is implemented in LLVM and its hardware in an industrial sub-28nm process. RipTide compiles applications written in C while saving 25% energy vs. the state-of-the-art ULP CGRA and 6.6x energy vs. a von Neumann core.

Abstract Author(s): Graham Gobieski, Souradip Ghosh, Tony Nowatzki, Todd C. Mowry, Nathan Beckmann, Brandon Lucia